Today's world of mobile electronics is driven by devices that are inherently expected to provide high speed, high performance, and low leakage . Such growing demand for high-performance devices is catalyzing the aggressive scaling of transistors below 22 nm. However, the relentless miniaturization of transistor dimensions has resulted in increased static power dissipation due to leakage current at a horrendous rate. Say no to plagiarism. Get a tailor-made essay on “Why Violent Video Games Should Not Be Banned”? Get an original essay. Additionally, the physical constraints of achieving very large scale dimensions such as steep doping profiles, lithography alignment, and increased short channel effects due to inefficient gate control have limited the realization of transistors classical ultrascale planars. All these factors have outpaced the conventional single-gate planar transistors, thus shifting the attention of researchers towards multi-gate transistors which consume the minimum space on the semiconductor wafer as well as better performance through gate control effective. In the current field, 3D topologies such as Gate-all-around (GAA) nanowires (NWs) are considered the most promising ultimate short-channel device for future technologies [1]-[4]. to be extracted from a single nanowire is quite small and must therefore be stacked in arrays consuming the valuable surface area of ​​the chip, thus counteracting the advantage of reduced dimensions [5], [6]. Furthermore, this efficient gate control leads to a significant overlap of the valence band of the channel region with the conduction band of the drain in the OFF state regime, triggering side band-to-band tunneling (L-BTBT). electrons from the channel to the drain [4][6-16]. However, the gate-induced drain leakage current induced by classical transverse BTBT (T-BTBT) appears due to the tunneling of electrons from the valence band to the conduction band in the gate-drain overlap region through the band mechanism to band tunneling (BTBT) and trap-assisted tunneling (TAT) and is dominant in large negative gate biases [4][17],[18]. Therefore, shipping FETs with improved output drive current from 3D topologies with better ION/IOFF ratio resulted in the invention of silicon nanotubes with core-shell-gate stacking [19-27 ]. Such nanotube architecture provides the best possible electrostatic gate control, which not only provides immunity to short channel effects but also results in higher drive current due to effective volume inversion compared to nanowires as well as efficient use of space. 19-22]. However, this ultimate gate control in the NT architecture results in an enhanced L-BTBT mechanism due to the presence of the central gate [27]. Therefore, the enhanced L-BTBT in nanotubes increases their current in the OFF state, degrading their ION/IOFF ratio. Additionally, L-BTBT is more pronounced at scaled dimensions, which prevents their scaling to future technology nodes and makes their use impractical for high performance. computing as well as low-consumption applications. Therefore, L-BTBT needs to be mitigated and this problem has been neglected until now. Keep in mind: this is just a sample. Get a personalized article from our expert writers now. Get a Custom Essay Therefore, in this work, we propose the use of a dual material gate (DMG) in both the